Onward and upward to smaller faster devices

As digital technology infiltrates every aspect of modern life, the need expands for more powerful, efficient and compact electronic devices. Researchers at KAUST have taken transistor design into a new dimension by developing improved methods to stack transistors vertically instead of arranging them flat^[1].

Transistors are the tiny semiconductor switches that lie at the heart of all digital devices. Stacking them on top of one another could pack greater computing power into much smaller spaces.

“We hope our 10-stack transistor technology will pave the way toward the next generation of electronic devices that will be faster, more compact and more capable than ever before,” says Saravanan Yuvaraja, a postdoc working in Xiaohang Li’s research group.

Some approaches to 3-D stacking of transistors have already been explored, but the new technology has surpassed earlier methods in many aspects, including faster switching, lower power consumption and improved performance. The ability to incorporate different transistor architectures and logic gates within the same stack allows complex circuits to be created with readily fine-tuned electrical characteristics.

Yuvaraja explains that the possibilities for building the vertically stacked transistors emerged from studying the potential of specific semiconductor materials, such as indium oxide (In₂O₃). These have excellent electronic properties and can be readily processed at room temperature.

The researchers’ key innovation was to adapt existing thin-film transistor fabrication technology to integrate 10 layers of indium oxide transistors into compact single block (monolithic) vertical stacks. The stacked transistors are carried on a conventional silicon/silicon dioxide wafer, with the environmentally friendly polymer Parylene-C as insulating layers within the stacks.

It was essential that the team’s approach was compatible with current manufacturing processes to ensure the innovative stacked architecture would be practical and scalable.

The journey was far from easy. Yuvaraja says: “Numerous challenges required persistent effort, innovative thinking and meticulous work to overcome the hurdles that arose at each stage.” Particular challenges included finding materials that would stack together as required, developing appropriate lithography techniques and designing effective testing procedures.

Li comments: “Our achievement offers significant improvements over existing alternatives and sets a new benchmark in semiconductor technology. It is highly scalable both in the X-Y plane and along the Z axis, which is crucial for the continuation of Moore’s Law.” Moore’s Law suggests that as components — such as transistors in integrated circuits — become smaller and faster, it will enable computers and computing power to become smaller, faster and more cost-effective.

The team now plans for further miniaturization of the technology, while also investigating new ways to improve efficiency and performance even more. They anticipate that this work could impact a wide variety of applications, including high-performance computing, next-generation mobile and wearable technology, and many medical devices.